Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 826

Index
IRPTL register, 10-33
IRQ2-0 pins, 15-12
IRQxE (interrupt sensitivity) bits,
IRQxE (interrupt x edge/level sensitivity)
bits, 3-53
IRQxI (hardware interrupt) bits,
ISSEN bit, 10-37, 10-40
ISSS bit, A-95
IVT bit, A-45
Ix (index) registers, 4-2, 4-16,
Ix registers, G-5
J
JTAG
instruction register codes,
interface, access to features,
interface pins, 15-12
logic, 6-1
port, 1-2, 6-1, G-6
specification, IEEE 1149.1, 6-1, 6-2,
test access port (TAP),
test-emulation port,
JTAG ICE, 6-1
JTAG instruction
EMUPID, 6-5
JUMP instructions, 3-1, 3-11,
loop abort (LA) register,
pops status stack with (CI),
K
known duration accesses,
L
LADDR register, 3-64,
LAFS bit, 9-55, A-77
LA register, 3-26
I-16
A-8
A-28
A-37
6-6
6-3
6-9
6-1
6-1 to 6-10
G-6
3-26
3-57
8-20
A-35
ADSP-2126x SHARC Processor Hardware Reference
latch
characteristics, 6-2
status for interrupts,
latches, high and low priority,
latching interrupts, 3-55
latchup, 15-14
latency, 3-9, 3-50, 3-63
input synchronization,
I/O processor registers,
one cycle, 7-8
system registers, 3-63
LCNTR (loop counter) register, 3-25,
3-33, 3-34, 3-64,
Least Significant Bits (LSB),
left-justified sample pair mode, 9-9, 9-14,
9-15, 9-16, 9-17, 9-18, 9-20,
control bits, 9-15
SPCTLx control bits,
Tx/Rx on FS falling edge,
Tx/Rx on FS rising edge,
LEFTO operation, A-14
LEFTZ (shifter) operation,
less or equals (LE) condition,
less than (LT) condition,
level sensitive interrupts, 3-53, A-8,
LFS, LTFS and LTDV bit, 9-55, A-77,
A-147
link buffer DMA enable See LxDEN bit
link port, 1-17
enhancements, 1-17
LIRPTL (interrupt latch/mask) registers,
3-54, 3-55, 3-64
LIRPTL (interrupt) registers,
LIRPTL registers, 10-33
LMFS bit, 9-27
loader kernel, 15-21
logical operations, 2-17
logical shifts, G-9
A-25
12-29
15-12
A-62
A-36
3-6
12-2
9-11
9-10
9-10
A-14
3-19
3-19
G-6
A-30