Sport Control Registers And Data Buffers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPORT Control Registers and Data Buffers

4. Wait one cycle. A
a is not inserted, the processor core is paused for one cycle any-
NOP
way. This allows the serial port companding hardware to reload the
transmit buffer with the companded value.
5. Read the 8-bit companded value from the transmit buffer.
To expand data in place, use the same sequence of operations (above) with
the receive buffer instead of the transmit buffer. When expanding data in
this way, set the appropriate serial word length (
trol register.
With companding enabled, interfacing the serial port to a codec requires
little additional programming effort. If companding is not selected, two
formats are available for received data words of fewer than 32 bits—one
that fills unused MSBs with zeros, and another that sign-extends the MSB
into the unused bits.
SPORT Control Registers and Data Buffers
The ADSP-2126x has six serial ports. Each SPORT has two data paths
corresponding to channel A and channel B. These data buffers are
and (primary) and
RXSPxA
B in all six SPORTS operate synchronously to their respective
and signals. Companding is supported only on primary A channels.
FSx
The registers used to control and configure the serial ports are part of the
IOP register set. Each SPORT has its own set of 32-bit control registers
and data buffers. The SPORT registers are described in
The SPORT control registers are programmed by writing to the appropri-
ate address in memory. The symbolic names of the registers and individual
control bits can be used in programs. The definitions for these symbols are
contained in the file
9-44
instruction can be used to cause this delay; if
NOP
and
TXSPxB RXSPxB
located in the
def2126x.h
ADSP-2126x SHARC Processor Hardware Reference
) in the
SLEN SPCTLx
(secondary). Channel A and
SPORTx_CLK
Table 9-5.
directory of the
INCLUDE
Con-
TXSPxA