Master Mode Operation - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

resistor is required on both the
selected.
When the
OPD
pin is three-stated when the data driven out on
pin is not three-stated when the driven data is logic-low. A zero is
MOSI
driven on the
MOSI
port is configured as a slave, the
out on is logic-high.
MISO

Master Mode Operation

When the SPI is configured as core master (and DMA mode is not
selected), the SPI port should be configured and transfers started using the
following steps:
1. When
CPHASE
trolled by the SPI port. Otherwise [
controlled by the core, and user software controls the pins through
the
SPIFLGx
specify which slave-select signal to use by writing to the
ister, setting one or more of the SPI Flag Select bits (
2. Write to the
master and configuring the SPI system by specifying the appropri-
ate word length, transfer format, baud rate, and other necessary
information.
3. If
CPHASE
desired slaves by clearing one or more of the SPI flag bits (
in the
SPIFLG
4. Initiate the SPI transfer. The trigger mechanism for starting the
transfer is dependant upon the
See Table 10-1 on page 10-16
ADSP-2126x SHARC Processor Hardware Reference
MOSI
is set and the SPI port is configured as a master, the
pin in this case. Similarly, when
MISO
is set to 0, the slave selects are automatically con-
bits. Before enabling the SPI port, programs should
and
SPICTL SPIBAUD
= 1 (user-controlled slave-select signals), activate the
register.
Serial Peripheral Interface Port
and pins when this option is
MISO
is logic-high. The
MOSI
OPD
pin is three-stated if the data driven
= 1] the slave selects are
CPHASE
registers, enabling the device as a
bits in the
TIMOD
for details.
MOSI
is set and the SPI
reg-
SPIFLG
).
DSxEN
)
SPIFLG
register.
SPICTL
10-9