SPI Interface Signals
requires these signals to be manually controlled in software via the
bits in the
SPIFLG
SPI Device Select Signal
The
signal is the Serial Peripheral Interface Device Select Input sig-
SPIDS
nal. This is an active low signal used to enable an ADSP-2126x configured
as a slave device. This input-only pin behaves like a chip select, and is pro-
vided by the master device for the slave devices. When the processor is the
SPI-master in a multimaster environment, the
signal. In multimaster mode, if the
asserted (driven low), an error has occurred. This means that another
device is also trying to be the master device.
Master Out Slave In (MOSI)
The
pin is one of the bidirectional I/O data pins. If the processor is
MOSI
configured as a master, the
If the processor is configured as a slave, the
receive (input) pin. In an ADSP-2126x processor SPI interconnection, the
data is shifted out from the
the
input of the slave.
MOSI
Master In Slave Out (MISO)
The
pin is one of the bidirectional I/O data pins. If the ADSP-2126x
MISO
is configured as a master, the
If the ADSP-2126x is configured as a slave, the
transmit (output) pin. In an SPI interconnection, the data is shifted out
from the
MISO
of the master.
Only one slave is allowed to transmit data at any given time.
illustrates how the ADSP-2126x can be used as the slave SPI device. The
10-6
register (the
SPIDSx
pin becomes a data transmit (output) pin.
MOSI
MOSI
MISO
output pin of the slave and shifted into the
ADSP-2126x SHARC Processor Hardware Reference
bits are ignored when
SPIDS
input signal of a master is
SPIDS
pin becomes a data
MOSI
output pin of the master and shifted into
pin becomes a data receive (input) pin.
MISO
SPIDSx
=0).
CPHASE
pin acts as an error
pin becomes a data
input pin
MISO
Figure 10-4
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