Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 8

Contents
Case #4: External Memory or IOP Memory Space Data Move 3-44
Example: Register-to-Memory Moves - External or IOP Memory
Space Data Move ....................................................... 3-44
Case #5: Uncomplimentary Register Data Move ................ 3-45
Conditional DAG Operations ............................................... 3-45
Timer and Sequencing ................................................................ 3-46
Interrupts and Sequencing .......................................................... 3-48
Delayed Interrupt Processing ................................................. 3-52
Sensing Interrupts ................................................................. 3-53
Masking Interrupts ............................................................... 3-54
Latching Interrupts ............................................................... 3-55
Stacking Status During Interrupts .......................................... 3-56
Nesting Interrupts ................................................................. 3-58
Reusing Interrupts ................................................................ 3-60
Interrupting IDLE ................................................................ 3-61
Summary .................................................................................... 3-61
DATA ADDRESS GENERATORS
Setting DAG Modes ..................................................................... 4-4
Circular Buffering Mode ......................................................... 4-5
Broadcast Loading Mode ......................................................... 4-5
Alternate (Secondary) DAG Registers ...................................... 4-6
Bit-Reverse Addressing Mode .................................................. 4-8
Using DAG Status ........................................................................ 4-9
viii ADSP-2126x SHARC Processor Hardware Reference