Timer Configuration Registers (Tmxctl) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

Timer Configuration Registers (TMxCTL)

All timer clocks are gated off when the specific timer's configuration regis-
ter is set to zero at system reset or subsequently reset by user programs.
These registers are shown in
15 14 13 12
IRQEN
Interrupt Enable
PRDCNT
Period Count
Figure A-68. TMxCTL Register
Table A-49. TMxCTL Register Bit Descriptions
Bit
1–0
2
3
4
A-158
Figure
11 10 9 8 7 6
Name Definition
TIMODE Timer Mode.
00 = Reset
01 = PWM_OUT mode (TIMODEPWM)
10 = WDTH_CAP mode (TIMODEW)
11 = EXT_CLK mode (TIMODEEXT)
PULSE Pulse Edge Select.
1 = Positive active pulse
0 = Negative active pulse
PRDCNT Period Count.
1 = Count to end of period
0 = Count to end of width
IRQEN Interrupt Enable.
1 = Enable
0 = Disable
ADSP-2126x SHARC Processor Hardware Reference
A-68.
5 4 3 2 1 0
TIMODE (1–0)
Timer Mode
PULSE
Pulse Edge Select