Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 804

DMA TCB chain loading. This is the process that the I/O processor uses
for loading the TCB of the next DMA sequence into the parameter regis-
ters during chained DMA.
Edge-sensitive interrupt. The DSP detects this type of interrupt if the
input signal is high (inactive) on one cycle and low (active) on the next
cycle when sampled on the rising edge of CLKIN.
Endian Format, Little Versus Big. The DSP uses big-endian format—
moves data starting with most-significant-bit and finishing with least-sig-
nificant-bit—in almost all instances. The two exceptions are bit order for
data transfer through the serial port and word order for packing through
the parallel port. For compatibility with little-endian (least-signifi-
cant-first) peripherals, the DSP supports both big- and little-endian bit
order data transfers. Also for compatibility little endian hosts, the DSP
supports both big and little endian word order data transfers.
Explicit Versus Implicit operations. In SIMD mode, identical instruc-
tions execute on the PEx and PEy computational units; the difference is
the data. The data registers for PEy operations are identified (implicitly)
from the PEx registers in the instruction. This implicit relation between
PEx and PEy data registers corresponds to complementary register pairs.
Field deposit (Fdep) instructions. These shifter instructions take a group
of bits from the input register (starting at the LSB of the 32-bit integer
field) and deposit the bits as directed anywhere within the result register.
Field extract (Fext) instructions. These shifter extract a group of bits as
directed from anywhere within the input register and place them in the
result register (aligned with the LSB of the 32-bit integer field).
Programmable Flag pins. These pins (FLAGx) can be programmed as
input or output pins using bit settings in the MODE2 register. The status
of the flag pins is given in the FLAGS or IOFLAG register.
General purpose input/output pins. See Programmable Flag pins.
G-4 ADSP-2126x SHARC Processor Core Manual