Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 350

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Parallel Port Programming Examples

dm(EIPP) = r1;

dm(PPCTL)= ustat3;

dm(TXPP) = r2;

/* -----14 core cycles (minimum) available while each word is

being transmitted. Writing to PPCTL has a 2 cycle effect-latency,

so the result of writing this register in the 14th cycle doesn't

take effect until the 16th cycle - which is one cycle after the

cycle completes----- */

/* (NOTE: Modifying PP parameters before 14 cycles have passed

will cause the access to fail - Using more than 14 cycles is

update addr and data for next loop iteration:

r1 = R1 + r0;

r2 = r2 + 1;

/*-----------------------------------------------------------*/

dm(PPCTL)=ustat4;

/* NOTE: PPEN must be cleared before modifying EIPP /*

========================================================

/* enable PP */

<-- write to PP FIFO */

/* next ext. destination address += 4

/* next data to write /*

<-- 14 cycles later, it's safe to

disable/alter PP because each access takes

15 CCLK cycles, and writing PPCTL has a

2-cycle effect-latency. */

ADSP-2126x SHARC Processor Hardware Reference

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