Selecting Frame Sync Options (Difs); Enabling Sport Dma (Sden) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPORT Operation Modes
To select the channel order, set the
the left channel first, or clear the
the right channel first.

Selecting Frame Sync Options (DIFS)

When using both SPORT channels (
mitters and
MSTR
frame sync signal only when both transmit buffers contain data because
both transmitters share the same
ous transmission, both transmit buffers must contain new data.
When using both SPORT channels (
ers and = 1,
MSTR
sync signal only when both receive buffers are not full because they share
the same
SPORTx_CLK
When using both SPORT channels as transmitters and
= 1 and
SPTRAN
frequency set by
data. The DMA controller or the application is responsible for filling the
transmit buffers with data.
When using both SPORT channels as receivers and
and = 1, the processor generates a frame sync signal at the frequency
DIFS
set by , irrespective of the receive buffer status. Bits 31–16 of the
FSDIV
register comprise the
Divisor Registers (DIVx)" on page A-86.

Enabling SPORT DMA (SDEN)

DMA can be enabled or disabled independently on any of the SPORT's
transmit and receive channels.
Between SPORTS and Internal Memory" on page 9-65.
(=1) to enable DMA and set the channel in DMA-driven data
SDEN_B
9-22
FRFS
= 1, = 1, and
SPTRAN
SPORTx_CLK
= 0, and
SPTRAN DIFS
and
SPORTxFS
= 1, the processor generates a frame sync signal at the
DIFS
whether or not the transmit buffers contain new
FSDIVx
bit field.
FSDIV
For more information, see "Moving Data
ADSP-2126x SHARC Processor Hardware Reference
bit (= 1) to transmit or receive on
FRFS
bit (= 0) to transmit or receive on
and
SPORTx_DA SPORTx_DB
= 0, the processor generates a
DIFS
and
SPORTx_FS
and
SPORTx_DA SPORTx_DB
= 0, the processor generates a frame
.
MSTR
For more information, see "SPORT
) as trans-
. For continu-
) as receiv-
= 1,
MSTR
= 1, = 0
SPTRAN
DIV
Set or
SDEN_A