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i4 = tx_buf2a;
m4 = 1;
i12 = rx_buf3a;
m12 = 1;
SPORT_DMA_setup:
/* set internal loopback bit for SPORT2 & SPORT3 */
bit set ustat3 SPL;
dm(SPMCTL23) = ustat3;
/* Configure SPORT2 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV = [fCCLK(200MHz)/4 x FSCLK(20MHz)] – 1 = 0x004 */
/* FSDIV = [FSCLK(20 MHz)/TFS(.625 MHz)] – 1 = 31 = 0x001F */
R0 = 0x001F0004;
ustat4 = SPEN_A|
SLEN32|
FSR|
SPTRAN|
IFS|
ICLK;
dm(SPCTL2) = ustat4;
/* Configure SPORT3 as a receiver */
/* externally generating clock and frame sync */
r0 = 0x0;
ustat3 = SPEN_A|
SLEN32|
FSR;
dm(SPCTL3) = ustat3;
/* Set up loop to transmit and receive data */
lcntr = LENGTH(tx_buf2a), do (pc,4) until lce;
/* Retrieve data using DAG1 and send TX via SPORT2 */
ADSP-2126x SHARC Processor Hardware Reference
dm(DIV2) = R0;
/* Enable Channel A */
/* 32-bit word length */
/* Frame Sync Required */
/* Transmit on enabled channels */
/* Internally Generated Frame Sync */
/* Internally Generated Clock */
dm(DIV3) = R0;
/* Enable Channel A */
/* 32-bit word length */
/* Frame Sync Required */
Serial Ports
9-81
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