Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 670

Core Registers
BRKCTL (0x30025)
(Bits 15-0)
NEGIA3
Negate Instruction Address
Breakpoint #3
1=Enable Breakpoint
0=Disable Breakpoint
NEGIA2
Negate Instruction Address
Breakpoint #2
1=Enable Breakpoint
0=Disable Breakpoint
NEGIA1
Negate Instruction Address
Breakpoint #1
1=Enable Breakpoint
0=Disable Breakpoint
NEGDA2
Negate DM Address Breakpoint #2
1=Enable Breakpoint
0=Disable Breakpoint
NEGDA1
Negate DM Address Breakpoint #1
1=Enable Breakpoint
0=Disable Breakpoint
NEGPA1
Negate PM Address Breakpoint #1
1=Enable Breakpoint
0=Disable Breakpoint
Figure A-15. BRKCTL Register (Lower Bits)
Table A-16. BRKCTL Register Bit Descriptions
Bit # Name
1–0 PA1MODE
3–2 DA1MODE
A-48
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
Function
PA1Triggering Mode
00 = Breakpoint Disabled
01 = WRITE Access
10 = READ Access
11 = Any access
DA1 Triggering Mode
00 = Breakpoint Disabled
01 = WRITE Access
10 = READ Access
11 = Any access
ADSP-2126x SHARC Processor Hardware Reference
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
PA1MODE
PA1 Triggering Mode
00=Breakpoint Disabled
01=WRITE Access
10=READ Access
11=Any Access
DA1MODE
DA1 Triggering Mode
00=Breakpoint Disabled
01=WRITE Access
10=READ Access
11=Any Access
DA2MODE
DA2 Triggering Mode
00=Breakpoint Disabled
01=WRITE Access
10=READ Access
11=Any Access
IO1MODE
IO1 Triggering Mode
00=Breakpoint Disabled
01=WRITE Access
10=READ Access
11=Any Access