Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 820

Index
extended precision normal word, 5-12,
5-25
data access, 5-48, 5-49
data storage, 5-2
mixed data access, 5-25
SISD mode access, 5-51
external device or memory
reading from, 8-6
writing to, 8-7
external event watchdog (EXT_CLK)
mode, 14-1, 14-13
external memory, 1-16
access modes, G-6
DMA count See ECEPx registers
DMA index See EIPP register
DMA modifier See EMEPx registers
external port, 1-12, 8-1
enhancements, 1-16
modes, 8-5
EXTEST instruction, 6-6
extract bit field, 2-31
extract exponent, 2-31
F
FADDR register, 3-2, 3-64,
Falling Edge Interrupt Mask
(DAI_IRPTL_FE) register,
false always (FOREVER) Do/Until
condition, 3-20
fetch address (FADDR) register, 3-2,
fetch address See FADDR register
fetch cycle, 3-4
fetched address, 3-2
field deposition/extraction,
I-10
A-35
A-169
3-64
G-9
ADSP-2126x SHARC Processor Hardware Reference
FIFO
control and status, 11-14
controlling, 11-14
FIFOFLSH bit, A-105
memory data transfer,
overflow clear bit, 11-14
SPI DMA, 10-46, 10-54
to memory data transfer,
FIFOFLSH bit, A-105
fixed-point
ALU instructions, 2-21
data, G-1
multiplier instructions, 2-29,
operands, 2-18, A-12
operations, 2-39
overflow interrupt (FIXI) bit,
saturation values, 2-26
fixed-point overflow interrupt (FIXI) bit,
3-55
flag
errors See DMA, external port, host port,
serial port, SPI port, and UART port
input (FLGx_IN) conditions,
input/output See FLAGx pins
input/output signals See FLAGx pins
input/output value (FLAGS) register,
3-64
input/output value See FLAGS register
slave device select See DSxEN(3-0)
slave See DSxEN bits
update, 2-20, 2-28, 2-35, 2-36, 2-50,
3-55, 4-9, 5-22, G-5
flag input (FLGx_IN) conditions,
flag input/output See FLAGx pins
flags, DAI, 12-26
FLAGS register, 3-64,
Flag Value (FLAGS) register,
FLAGx pins, 9-8, 10-3, 15-12,
11-15
11-15
2-43
A-29
3-20
3-20
A-39
A-39
A-41