Slave Transfer Preparation - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPI Data Transfer Operations
3. Write to the
configure:
• A receive access (
• A transmit access (
If DMA chaining is desired, set the
SPIDMAC

Enable the SPI port before enabling DMA to avoid data
corruption.

Slave Transfer Preparation

When enabled as a slave, the device prepares for a new transfer according
to the function and actions described in
The following steps illustrate the SPI receive or transmit DMA sequence
in an SPI slave in response to a master command:
1. Once the slave-select input is active, the processor starts receiving
and transmitting data on active
channel (
the IOP. The function of the other channel is dependant on the
and
SENDZ
2. Reception or transmission continues until the SPI DMA word
count register transitions from 1 to 0.
3. A number of conditions can occur while the processor is configured
for Slave mode:
• If the DMA engine cannot keep up with the receive data
stream during receive operations, the receive buffer operates
according to the state of the
10-18
register to enable the SPI DMA engine and
SPIDMAC
SPIRCV
SPIRCV
register.
or ) is automatically transferred to/from memory by
TX RX
bits in the
SPICTL
ADSP-2126x SHARC Processor Hardware Reference
= 1) or
= 0)
SPICHEN
Table 10-1.
edges. The data for one
SPICLK
register.
bit in the
GM
bit in the
GM
register.
SPICTL