32-Bit Normal Word Addressing Of Single-Data In Sisd Mode - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory Access Listings
32-Bit Normal Word Addressing of Single-Data in
SISD Mode
Figure 5-15 shows the SISD, single-data, 32-bit normal word addressed
access mode. For normal word addressing, the processor treats the data
buses as two 32-bit normal word lanes. The 32-bit value for the normal
word access completes a transfer using the least significant normal word
lane of the PM or DM data bus. The processor drives the other normal
word lanes of the data buses with zeros.
In SISD mode, the instruction accesses a
accesses
WORD X0
cant address bit. The other access within this four column location has an
address with a least significant bit of "1" and selects
ory. The syntax targets register

For normal word accesses, the processor zero-fills the least signifi-
cant 8 bits of the data register on loads and truncates these bits on
stores to memory.
5-40
whose normal word address has "0" for its least signifi-
in
RX
ADSP-2126x SHARC Processor Hardware Reference
register. This instruction
PEx
WORD X1
.
PEx
from mem-