Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 10

Contents
Internal Memory Data Width ................................................ 5-18
Secondary Processor Element (PEy) ....................................... 5-19
Broadcast Register Loads ....................................................... 5-20
Illegal I/O Processor Register Access ...................................... 5-21
Unaligned 64-Bit Memory Access .......................................... 5-21
Using Memory Access Status ....................................................... 5-22
Accessing Memory ...................................................................... 5-22
Access Word Size ................................................................... 5-23
Long Word (64-Bit) Accesses ............................................ 5-23
Instruction and Extended-Precision Normal Word Accesses 5-25
Normal Word (32-Bit) Accesses ........................................ 5-26
Short Word (16-Bit) Accesses ............................................ 5-26
Setting Data Access Modes .................................................... 5-27
SYSCTL Register Control Bits .......................................... 5-27
Mode 1 Register Control Bits ............................................ 5-27
Mode 2 Register Control Bits ............................................ 5-28
SISD, SIMD, and Broadcast Load Modes .............................. 5-28
Single- and Dual-Data Accesses ............................................. 5-28
Instruction Examples ........................................................ 5-29
Shadow Write FIFO ................................................................... 5-29
Internal Memory Access Listings ................................................. 5-30
Short Word Addressing of Single-Data in SISD Mode ............ 5-32
Short Word Addressing of Dual-Data in SISD Mode .............. 5-34
Short Word Addressing of Single-Data in SIMD Mode .......... 5-36
x ADSP-2126x SHARC Processor Hardware Reference