Dma Block Transfers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Moving Data Between SPORTS and Internal Memory
port DMA is not enabled, the SPORT generates an interrupt every time it
receives or starts to transmit a data word. The processor's on-chip DMA
controller handles the DMA transfer, allowing the processor core to con-
tinue running until the entire block of data is transmitted or received.
Service routines can then operate on the block of data rather than on sin-
gle words, significantly reducing overhead.

Standard DMA does not function properly in I
mode when two channels (A and B) are enabled with different
DMA count values. In this case, the interrupt is generated for the
least (smallest) count only. If both the A and B channels of the
SPORTs are used in I
then the DMA count value should be the same for both channels.
This does not apply to chained DMA.

DMA Block Transfers

The processor's on-chip DMA controller allows automatic DMA transfers
between internal memory and each of the two channels of each serial port.
Each SPORT has two channels for transferring data, and each can be con-
figured to receive or to transmit. There are twelve DMA channels for serial
port operations. The serial port DMA channels are numbered as shown in
Table 9-8.
9-66
2
S/left-justified mode with DMA enabled,
ADSP-2126x SHARC Processor Hardware Reference
2
S/left-justified