Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 369

2
The I S bus transmits audio data and control signals over separate lines.
The data line carries two multiplexed data channels—the left channel and
the right channel. In I
transmit, then SPORT transmit channels (
simultaneously, each transmitting left and right I
channels on a SPORT are set up to receive, the SPORT receive channels
( and
RXSPxA RXSPxB
2
I S channels. Data is transmitted in MSB-first format.

SHARC SPORTs are designed such that in I
LRCLK is held at the last driven logic level and does not transition,
to provide an edge, after the final data word is driven out. There-
fore, while transmitting a fixed number of words to an I
that expects an LRCLK edge to receive the incoming data word,
the SPORT should send a dummy word after transmitting the
fixed number of words. The transmission of this dummy word tog-
gles LRCLK, generating an edge. Transmission of the dummy
word is not required when the I

If the
MCEA
SPEN_A

Multichannel operation and companding are not supported in I
mode. See
Each SPORT transmit or receive channel has a channel enable, a DMA
enable, and chaining enable bits in its
signal is used as the transmit and/or receive word select signal.
SPORTx_FS
DMA-driven or interrupt-driven data transfers can also be selected using
bits in the
SPCTLx
ADSP-2126x SHARC Processor Hardware Reference
2
S mode, if both channels on a SPORT are set up to
) receive simultaneously, each receiving left and right
or bits are set (=1) in the
MCEB
and bits in the
SPEN_B
"Multichannel Operation" on page
register.
and
TXSPxA TXSPxB
2
S channels. If both
2
S master mode,
2
S receiver is a SHARC SPORT.
SPMCTLxy
register must be cleared (=0).
SPCTL
9-24.
Control register. The
SPCTLx
Serial Ports
) transmit
2
S receiver
register, the
2
S
9-19