Input Synchronization Delay; Clock Derivation - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Pin Descriptions

If the system clock to the
register,

Input Synchronization Delay

The processor has several asynchronous inputs—
pins and
FLG15-0
asserted in arbitrary phase to the processor clock,
synchronizes the inputs prior to recognizing them. The delay associated
with recognition is called the synchronization delay.
Any asynchronous input must be valid prior to the recognition point in a
particular cycle. If an input does not meet the setup time on a given cycle,
it may be recognized in the current cycle or during the next cycle.
To ensure recognition of an asynchronous input, it must be asserted for at
least one full processor cycle plus setup and hold time, except for
which must be asserted for at least four processor cycles. The minimum
time prior to recognition (the setup and hold time) is specified in the data
sheet.

Clock Derivation

The processor uses a PLL on the chip, to provide clocks that switch at
higher frequencies than the system clock (
methodology used influences the clock frequencies and behavior for the
serial, SPI, and parallel ports, in addition to the processor core and inter-
nal memory. In each case, the processor PLL provides a non-skewed clock
to the port logic and I/O pins.
The PLL provides a clock that switches at the processor core frequency to
the serial ports. Each of the serial ports can be programmed to operate at
clock frequencies derived from this clock. The six serial ports' transmit
and receive clocks are divided down from the processor core clock fre-
quency by setting the
15-4
SPICLK
are not usable.
FLG0–3
(when configured as inputs). These inputs can be
registers appropriately.
DIVx
ADSP-2126x SHARC Processor Hardware Reference
module is shut off in the
,
RESET TRST
. The processor
CLKIN
). The PLL-based clocking
CLKIN
PMCTL
, , DAI
IRQ2–0
,
RESET