Pulse Width - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

CLOCK INPUT
(FOR BO TH CLO CK
AND FRAME SYNC)
CLO CK OUTPUT
FRAME SYNC OUTPUT
(PHASE SHIFT = DIVISOR -1)
FRAME SYNC OUTPUT
(PHASE SHIFT = 0)
FRAME SYNC OUTPUT
(PHASE SHIFT = 1)
FRAME SYNC OUTPUT
(PHASE SHIFT = 2)
ENABLE
OTHER VALUES:
CLOCK DIVISOR = 2
FRAME SYNC DIVISOR = 8

PULSE WIDTH = 4

Figure 13-3. Adjusting Frame Sync Phase Shift
Pulse Width
Pulse width is the number of input clock periods for which the frame sync
output is . Pulse width should be less than the divisor of the frame
HIGH
sync. The pulse width of frame sync A is specified in bits 15–0 of the
register and the pulse width of frame sync B is specified in bits
PCG_PW
31–16 of the
PCG_PW
ADSP-2126x SHARC Processor Hardware Reference
register.
Precision Clock Generator
13-9