Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 463

format from the master may be changed between transfers to adjust to var-
ious requirements of a slave device.
When = 0, the slave select line,
CPHASE
between each word in the transfer. When
remain active (
Figure 10-7 shows the SPI transfer protocol for
starts toggling at the beginning of the data transfer,
SPICLK
= 1.
MSBF
CLO CK CYCLE
NUMBER
SPICLK
CLKPL = 0
SPICLK
CLKPL = 1
MOSI
FROM MASTER
*
MISO
FROM SLAVE
MSB
SPIDS
FROM MASTER
Figure 10-6. SPI Transfer Protocol for CPHASE = 0
ADSP-2126x SHARC Processor Hardware Reference
) between successive transfers or be inactive (
LOW
1 2 3
MSB 6
5
6 5
Serial Peripheral Interface Port
, must be inactive (
SPIDS
= 1,
CPHASE
CPHASE
4 5 6
4 3 2
4 3 2
)
HIGH
may either
SPIDS
).
HIGH
= 1. Note that
= 0, and
WL
7 8
1 LSB *
1 LSB *
* = UNDEFI NED
10-27