Mode Control 2 Register (Mode2 - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Table A-2. Mode Control 1 Register (MODE1) Bit Descriptions (Cont'd)
Bit Name
22 BDCST9
23 BDCST1
24 CBUFEN
31–25 Reserved

Mode Control 2 Register (MODE2)

The register is a non memory-mapped, universal, system register
MODE2
( and
Ureg Sreg
the register.
MODE2
ADSP-2126x SHARC Processor Hardware Reference
Description
Broadcast Register Loads Indexed With I9 Enable. Enables (broad-
cast I9 if set, = 1) or disables (no I9 broadcast if cleared, = 0) broad-
cast register loads for loads that use the data address generator I9
index.
When the BDCST9 bit is set, data register loads from the PM data
bus that use the I9 DAG2 Index register are "broadcast" to a register
or register pair in each PE.
Broadcast Register Loads Indexed With I1 Enable. Enables (broad-
cast I1 if set, = 1) or disables (no I1 broadcast if cleared, = 0) broad-
cast register loads for loads that use the data address generator I1
index.
When the BDCST1 bit is set, data register loads from the DM data
bus that use the I1 DAG1 Index register are "broadcast" to a register
or register pair in each PE.
Circular Buffer Addressing Enable. Enables (circular if set, = 1) or
disables (linear if cleared, = 0) circular buffer addressing for buffers
with loaded I, M, B, and L DAG registers.
). Figure A-2 and Table A-3
Registers Reference
provide bit information for
A-7