Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 650

Core Registers
Table A-9. IRPTL, IMASK, IMASKP Register Bit Descriptions
Bit Name
0 EMUI
1 RSTI
2 IICDI
3 SOVFI
4 TMZHI
5
SPERRI
6 BKPI
7 Reserved
8 I
IRQ2
9 I
IRQ1
10 I
IRQ0
A-28
Definition
Emulator Interrupt. An EMUI occurs when the external emulator
triggers an interrupt or the core hits a emulator breakpoint.
Note this interrupt has highest priority, it is read-only and non-mas-
kable
Reset Interrupt. An RSTI occurs as an external device asserts the
RESET pin or after a software reset (SYSCTL register). Note this
interrupt is read-only and non-maskable.
Illegal Input Condition Detected Interrupt. An IICDI occurs when a
TRUE results from the logical OR'ing of the illegal I/O processor reg-
ister access (IIRA) and unaligned 64-bit memory access bits in the
STKYx registers.
Stack Overflow/Full Interrupt. A SOVFI occurs when a stack in the
program sequencer overflows or is full.
Core Timer Expired High Priority. A TMZHI occurs when the timer
decrements to zero. Note that this event also triggers a TMZLI. Since
the timer expired event (TCOUNT decrements to zero) generates two
interrupts, TMZHI and TMZLI, programs should unmask the timer
interrupt with the desired priority and leave the other one masked.
Sport Error Interrupt. A SPERRI occurs on a FIFO underflow/over-
1
flow or a frame sync error.
Hardware Breakpoint Interrupt. When the processor is servicing
another interrupt, indicates if the BKPI interrupt is unmasked (if set,
= 1), or masked (if cleared, = 0).
Hardware Interrupt. An
the FLAG2 pin configured as
if interrupt latched on edge or level.
Hardware Interrupt. An
the FLAG2 pin configured as
if interrupt latched on edge or level.
Hardware Interrupt. An
the FLAG2 pin configured as
if interrupt latched on edge or level.
ADSP-2126x SHARC Processor Hardware Reference
I occurs when an external device asserts
IRQ2
. The E bit (MODE2) defines
IRQ2 IRQ2
I occurs when an external device asserts
IRQ1
. The E bit (MODE2) defines
IRQ1 IRQ1
I occurs when an external device asserts
IRQ0
. The E bit (MODE2) defines
IRQ0 IRQ0