Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 840

Index
SPIS0 bit, A-106
SPI slave mode operation,
SPISTAT register, 10-40, A-92,
SPI status See SPISTAT register
SPI transfer
beginning and ending,
formats, 10-26
SPI Transmit Data Buffer (TXSPI) register,
10-38, A-101
SPI (transmit/receive) finished See SPIF bit
SPI transmit underrun error See SPIUNF,
SPIUNFE bits
SPIUNF bit, 10-24, 10-25, 10-33, 10-40,
A-105
SPIUNF (SPI transmit underrun error) bit,
10-53, 10-54
SPMCTL01 register, 9-48
SPMCTL23 register, 9-45
SPMCTL45 register, 9-47
SPMCTLxy registers, A-79
SPORT
control registers, 9-44
data buffers, 9-44
DMA chaining, 9-73
DMA parameter register addresses,
DMA parameter registers,
interrupts, 9-64
loopback, 9-32
loopback mode, A-84
master mode (MSTR), enabling,
operation modes, left-justified sample
pair mode, 9-9, 9-14
operation modes, multichannel mode,
9-9, 9-24
operation modes, standard DSP serial,
9-9
2
operation modes (I S), 9-9,
OPMODE bit, 9-54
pairing, 9-25
receive buffer See RXSPx registers
I-30
10-44
A-101
10-28
9-70
9-69
9-16
9-18
ADSP-2126x SHARC Processor Hardware Reference
SPORT
registers, memory-mapped IOP
addresses, 9-45
registers. listed, 9-45
register writes, 9-50
transmit buffer See TXSPx registers
SPORT 0/1 multichannel control See
SPMCTL01 register
SPORT0 multichannel transmit compand
select x See MT0CCSx register
SPORT0 multichannel transmit select x See
MTxCSy registers
SPORT0 receive data buffer,
SPORT0 transmit data buffer,
SPORT1 receive data buffer,
SPORT1 transmit data buffer,
SPORT 2/3 multichannel control See
SPMCTL23 register
SPORT2 divisor for transmit/receive
SCLK2 and SFS2 See DIV2 register
SPORT2 multichannel transmit compand
select See MTxCSx register
SPORT2 receive data buffer,
A channel data See RXSP2A register
SPORT2 serial control See SPCTL2
register
SPORT2 transmit data buffer,
SPORT3 divisor for transmit/receive
SCLK3 and SFS3 See DIV3 register
SPORT3 receive data buffer, 9-46,
SPORT3 serial control See SPCTL3
register
SPORT3 transmit data buffer, 9-46,
SPORT 4/5 multichannel control See
SPMCTL45 register
SPORT4 divisor for transmit/receive See
DIV4 register
SPORT4 receive data buffer,
SPORT4 serial control See SPCTL4
register
(continued)
9-50
9-50
9-50
9-50
9-46
9-46
9-47
9-47
9-48