Memory - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

5 MEMORY

The ADSP-2126x contains a large, dual-ported internal memory for single
cycle, simultaneous, independent accesses by the core processor and I/O
processor. The dual-ported memory, in combination with three separate
on-chip buses, allow two data transfers from the core and one transfer
from the I/O processor in a single cycle. Using the I/O bus, the I/O pro-
cessor provides data transfers between internal memory and the DSP's
communication ports (serial ports and parallel port) without hindering the
DSP core's access to memory. This chapter describes the DSP's memory
and how to use it.
The DSP contains up to 2M bits of internal RAM and up to 4M bits of
internal ROM depending on the specific part number
block can be configured for different combinations of code and data stor-
age. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit
words. The DSP features a 16-bit floating-point storage format that effec-
tively doubles the amount of data that may be stored on-chip. A single
instruction converts the format from 32-bit floating-point to 16-bit
floating-point.
While each memory block can store combinations of code and data,
accesses are most efficient when one block stores data using the DM bus,
(typically block 1) for transfers, and the other block (typically block 0)
stores instructions and data using the PM bus. Using the DM bus and PM
bus with one dedicated to each memory block assures single-cycle execu-
tion with two data transfers. In this case, the instruction must be available
in the cache.
1
For specific memory information, see your ADSP-2126x product-specific data sheet.
ADSP-2126x SHARC Processor Hardware Reference
1
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