Spi Port Booting - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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Table of Contents

For a complete description of the Parallel Port Control register, see

lel Port Control Register (PPCTL)" on page

The parallel port DMA channel is used when downloading the boot kernel

information to the processor. At reset, the DMA Parameter registers are

initialized to the values listed in

Unlike previous SHARC processors, the ADSP-2126x does not

have a Boot Memory Select (

Table 15-8. Parameter Initialization Value

Parameter Register

SPI Port Booting

The ADSP-2126x supports booting from a host processor via SPI Slave

a host processor via SPI Master mode (

In both (master and slave) boot modes, the LSBF format is used

and SPI mode 3 is selected (clock polarity and clock phase = 1).

Both SPI boot modes support booting from 8-, 16-, or 32-bit SPI devices.

In all SPI boot mode, the data word size in the shift register is hardwired

Initialization Value

= 00), and booting from an SPI Flash, SPI PROM, or

ADSP-2126x SHARC Processor Hardware Reference

This is the offset from internal memory

normal word starting address of 0x80000.

This is the number of 32-bit words that are

equivalent to 256 instructions.

This is the number of bytes in 0x100

48-bit instructions.

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