Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 802

Buffered serial port. See Serial ports on page G-9.
Bus slave or slave mode. A DSP can be a bus slave to another DSP or to a
host processor. The DSP becomes a host bus slave when the HBG signal is
returned.
Circular buffer addressing. The DAG uses the Ix, Mx and Lx register set-
tings to constrain addressing to a range of addresses. This range contains
data that the DAG steps through repeatedly, "wrapping around" to repeat
stepping through the range of addresses in a circular pattern.
Companding (compressing/expanding). This is the process of logarithmi-
cally encoding and decoding data to minimize the number of bits that
must be sent.
Conditional branches. These are JUMP or CALL/return instructions
whose execution is based on testing an IF condition.
DAGEN, Data address generator. See Data Address Generator (DAG).
Data Address Generator (DAG). The data address generators (DAGs)
provide memory addresses when data is transferred between memory and
registers.
Data register file. This is the set of data registers that transfer data
between the data buses and the computation units. These registers also
provide local storage for operands and results.
Data registers (Dreg). These are registers in the PEx and PEy processing
elements. These registers are hold operands for multiplier, ALU, or shifter
operations and are denoted as Rx when used for fixed point operations or
Fx when used for floating-point operations.
Deadlock Resolution. When both the DSP subsystem and the system try
to access each other's bus in the same cycle, a deadlock may occur in
which neither access can complete. Techniques for resolving deadlock vary
with the interface: DRAM, host, or multiprocessor DSP.
G-2 ADSP-2126x SHARC Processor Core Manual