Port, Buffer, And Dma Control Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Setting Up DMA Parameter Registers

Port, Buffer, and DMA Control Registers

The Port, Buffer, and DMA Control Registers in
control registers for the ports and DMA channels. These registers include:
• Parallel Port Control register (
parallel port system, DMA, and external data width. It also config-
ures wait states, bus hold cycles and identifies the status of the
parallel port FIFO, internal, and external interfaces.
• Input Data Port Control register (
register for input data ports.
• Serial Port Control registers (
registers select the receive or transmit format, monitor FIFO status,
enable chaining, and start DMA for each serial port.
• SPI Port Control register (
ures and enables the SPI interface, selects the device as master or
slave, and determines the data transfer and word size. The
register also controls SPI DMA and FIFO status.
Table 7-4 shows the parameter registers for each DMA channel. These
registers function similarly to data address generator registers and include:
• Internal Index registers (
registers provide an internal memory address, acting as a pointer to
the next internal memory DMA read or write location.
• Internal Modify registers (
ify registers provide the signed increment by which the DMA
controller post-modifies the corresponding internal memory index
register after the DMA read or write.
• Count registers (
indicate the number of words remaining to be transferred to or
from internal memory on the corresponding DMA channel.
7-24
PPCTL
SPCTLx
SPICTL
,
IISPx
IMSPx
, ,
CSPx ICPP CSPI
ADSP-2126x SHARC Processor Hardware Reference
Figure 7-3
). This register enables the
). This is the control
IDP_CTL
, ). These control
SPMCTLxy
). This control register config-
, ,
IISPI IIPP IDP_DMA_Ix
, , ,
IMPP IMSPI IDP_DMA_Mx
, ). Count registers
IDP_DMA_Cx
shows the
SPIDMAC
). Index
). Mod-