Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 810

TCB chain loading. The process in which the DSP's DMA controller
downloads a Transfer Control Block from memory and autoinitializes the
DMA parameter registers.
Time Division Multiplexed (TDM) mode. The serial ports support TDM
or multichannel operations. In multichannel mode, each data word of the
serial bit stream occupies a separate channel— each word belongs to the
next consecutive channel so that, for example, a 24-word block of data
contains one word for each of 24 channels.
Transfer control block (TCB). A set of DMA parameter register values
stored in memory that are downloaded by the DSP's DMA controller for
chained DMA operations.
Tristate Versus Three-state. Analog Devices documentation uses the term
"three-state" instead of "tristate" because Tristate™ is a trademarked
term, which is owned by National Semiconductor.
Universal registers (Ureg). These are any processing element registers
(data registers), any Data Address Generator (DAG) registers, any pro-
gram sequencer registers, and any I/O processor registers.
Von Neumann architecture. This is the architecture used by most
(non-DSP) microprocessors. This architecture uses a single address and
data bus for memory access.
Wait states. The time spent waiting for an operation to take place. It may
refer to a variable length of time a program has to wait before it can be
processed, or to a fixed duration of time, such as a machine cycle.
When memory is too slow to respond to the CPU's request for it, wait
states are introduced until the memory can catch up.
G-10 ADSP-2126x SHARC Processor Core Manual