Twidiv Register; Slave Mode Control Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

TWIDIV Register

During master mode operation, the serial clock divider register (
values are used to create the high and low durations of the serial clock
( ). Serial clock frequencies can vary from 400 kHz to less than 20 kHz.
SCL
The resolution of the generated clock is 1/10 MHz or 100 ns.
= TWI
CLKDIV
For example, for an
an internal time reference of 10 MHz (period = 100 ns):
= 2500 ns ÷ 100 ns = 25
CLKDIV
For an with a 30% duty cycle, then
SCL
Note that
CLKLOW
Additional information for the
Divider Register (TWIDIV)" on page

Slave Mode Control Register

The TWI slave mode control register (
ated with slave mode operation. Settings in this register do not affect
master mode operation and should not be modified to control master
mode functionality.
Additional information for the
"Slave Mode Control Register (TWISCTL)" on page
ADSP-21368 SHARC Processor Hardware Reference
period ÷ 10 MHz time reference
SCL
of 400 kHz (period = 1/400 kHz = 2500 ns) and
SCL
and add up to
CLKHI
TWIDIV
TWISCTL
Two Wire Interface Controller
= 17 and
CLKLOW
.
CLKDIV
register bits can be found in
A-132.
) controls the logic associ-
TWISCTL
register bits can be found in
A-133.
)
TWIDIV
= 8.
CLKHI
"Clock
12-5