32-Bit Normal Word Addressing Of Single-Data In Simd Mode - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Internal Memory Access Listings
32-Bit Normal Word Addressing of Single-Data in
SIMD Mode
Figure 5-17 shows the SIMD, single-data, normal word addressed access
mode. For normal word addressing, the processor treats the data buses as
two 32-bit normal word lanes. The explicitly addressed (named in the
instruction) 32-bit value completes a transfer using the least significant
normal word lane of the PM or DM data bus. The implicitly addressed
(not named in the instruction, but inferred from the address in SIMD
mode) normal word value completes a transfer using the most significant
normal word lane of the PM or DM data bus.
In Figure 5-17, the explicit access targets the named register
implicit access targets that register's complementary register,
instruction uses a
the register
PEy
ter's complement,
complementary registers, see
page 5-19.
Figure 5-17 shows the data path for one transfer. The processor accesses
normal words sequentially in memory. For more information on arranging
data in memory to take advantage of this access pattern, see
on page 5-76.
5-44
register with an
PEx
as the explicit target, the processor would use that regis-
SX
, as the implicit target. For more information on
RX
"Secondary Processor Element (PEy)" on
ADSP-2126x SHARC Processor Hardware Reference
mnemonic. If the syntax named
RX
, and the
RX
. This
SX
Figure 5-40