Enhanced Emulation Status (Eemustat) Register; Boundary Register - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

JTAG Related Registers

Enhanced Emulation Status (EEMUSTAT) Register

The
EEMUSTAT
ADSP-2126x. This register is a memory-mapped IOP register. The pro-
cessor core can access this register. For I/O breakpoints, this register has
two status bits, one each for the two I/O buses (
When a breakpoint is hit, a user interrupt is generated. The breakpoint
status can be checked by looking at the
returns from interrupt, the breakpoint status bits will be cleared.

Boundary Register

The Boundary register is 163 bits long. This section defines the latch type
and function of each position in the scan path. The positions are num-
bered with 0 being the first bit output (closest to
last (closest to
following points in mind:
• Scan position 0 (
• Scan position 162 (
• Output enables:
1 = Drive the associated signals during the
instructions.
0 = Three-state the associated signals during the
instructions
• The
CLKIN
continues to clock the ADSP-2126x no matter which
CLKIN
instruction is enabled.
6-8
register acts as the breakpoint Status register for the
). When working with boundry scan registers keep the
TDI
CLK_CFG0
); this end is closest to
SPARE
signal can be sampled but not controlled (read-only).
ADSP-2126x SHARC Processor Hardware Reference
IOX
register. When the core
EEMUSTAT
TDO
); this end is closest to
EXTEST
and ).
IOY
) and 162 being the
(scan in first).
TDO
(scan in last).
TDI
and
INTEST
and
EXTEST INTEST