Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 745

Frame Sync Routing Control Registers
(SRU_FSx, Group C)
The Frame Sync Routing Control registers route frame sync, or a word
clock, to the serial ports and IDP. Each of the frame sync inputs specified
is connected to a frame sync source based on the values described in the
Group C frame sync sources listed in
frame sync sources can be connected using these registers:
•
SRU_FS0
•
SRU_FS1
•
SRU_FS2
SRU_FS0 (0x2450)
Reserved
SPORT5_FS_I
Serial Port 5 Frame Sync Input
15 14 13 12 11 10
1
SPORT2_FS_I
Serial Port 2 Frame Sync Input
Figure A-43. SRU_FS0 Register
ADSP-2126x SHARC Processor Hardware Reference
, described in Figure A-43
, described in Figure A-44
, described in Figure A-45
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 1 0 0 1 1 1
9 8
0 1 1 0 1 0 0
Registers Reference
Table A-36. Thirty-two possible
0 0 1 1 0 1 1
7 6 5 4 3 2 1 0
1 1 1 0 0 0 1 1
0
SPORT3_FS_I
Serial Port 3 Frame
Sync Input
SPORT4_FS_I
Serial Port 4 Frame
Sync Input
SPORT0_FS_I
Serial Port 0 Frame
Sync Input
SPORT1_FS_I
Serial Port 1 Frame
Sync Input
A-123