Active Low Versus Active High Frame Syncs; Sampling Edge For Data And Frame Syncs - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

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Frame Sync Options

Active Low Versus Active High Frame Syncs

Frame sync signals may be active high or active low (for example,

inverted). The

sync's logic level.

active high.

Active high frame syncs are the default. The

after a processor reset.

Active low or active high frame syncs are selected using the

bits. These bits are located in the

Data and frame syncs can be sampled on the rising or falling edges of the

serial port clock signals. The

selects the sampling edge.

For sampling receive data and frame syncs, setting

the processor selects the falling edge of

data and frame syncs. Note that transmit data and frame sync signals

change their state on the clock edge that is not selected.

For example, the transmit and receive functions of any two serial ports

connected together should always select the same value for

nally-generated signals are driven on one edge and received signals are

sampled on the opposite edge.

is cleared (=0), the corresponding frame sync signal is

is set (=1), the corresponding frame sync signal is active

ADSP-2126x SHARC Processor Hardware Reference

Control register determines the frame

bit is initialized to zero

Control registers.

for sampling receive

Control registers

is cleared (=0),

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