Table 7-5. DMA Channel Registers: Controls, Parameters
and Buffers (Cont'd)
DMA
Control
Channel
Registers
Number
4
SPCTL3
5
SPCTL3
6
SPCTL2
7
SPCTL2
8
SPCTL5
9
SPCTL5
10
SPCTL4
11
SPCTL4
12
IDP_CTL
13
IDP_CTL
14
IDP_CTL
15
IDP_CTL
16
IDP_CTL
17
IDP_CTL
ADSP-2126x SHARC Processor Hardware Reference
Parameter Registers
IISP3A, IMSP3A,
CSP3A, CPSP3A
IISP3B, IMSP3B,
CSP3B, CPSP3B
IISP2A, IMSP2A,
CSP2A, CPSP2A
IISP2B, IMSP2B,
CSP2B, CPSP2B
IISP5A, IMSP5A,
CSP5A, CPSP5A
IISP5B, IMSP5B,
CSP5B, CPSP5B
IISP4A, IMSP4A,
CSP4A, CPSP4A
IISP4B, IMSP4B,
CSP4B, CPSP4B
IDP_DMA_I0, IDP_D-
MA_M0, IDP_DMA_C0
IDP_DMA_I1, IDP_D-
MA_M1, IDP_DMA_C1
IDP_DMA_I2, IDP_D-
MA_M2, IDP_DMA_C2
IDP_DMA_I3, IDP_D-
MA_M3, IDP_DMA_C3
IDP_DMA_I4, IDP_D-
MA_M4, IDP_DMA_C4
IDP_DMA_I5, IDP_D-
MA_M5, IDP_DMA_C5
I/O Processor
Buffer Registers
Description
RXSP3A, TXSP3A
Serial Port 3A Data
RXSP3B, TXSP3B
Serial Port 3B Data
RXSP2A, TXSP2A
Serial Port 2A Data
RXSP2B, TXSP2B
Serial Port 2B Data
RXSP5A, TXSP5A
Serial Port 5A Data
RXSP5B, TXSP5B
Serial Port 5B Data
RXSP4A, TXSP4A
Serial Port 4A Data
RXSP4B, TXSP4B
Serial Port 4B Data
IDP_FIFO
DAI IDP Channel 0
IDP_FIFO
DAI IDP Channel 1
IDP_FIFO
DAI IDP Channel 2
IDP_FIFO
DAI IDP Channel 3
IDP_FIFO
DAI IPD Channel 4
IDP_FIFO
DAI IDP Channel 5
7-29
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