Interrupt Register (Lirptl) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Core Registers
Table A-9. IRPTL, IMASK, IMASKP Register Bit Descriptions (Cont'd)
Bit Name
28 SFT0I
29 SFT1I
30 SFT2I
31 SFT3I
1 The SPERRI interrupt (bit 5) is reserved for ADSP-21362/3/4/5/6 SHARC processors.

Interrupt Register (LIRPTL)

The register is a non-memory-mapped, universal, system register
LIRPTL
( and
Ureg Sreg
and displays mask pointers for interrupts.
vide bit definitions for the

The
MSKP
are for interrupt controller use only. Modifying these bits interferes
with the proper operation of the interrupt controller.
The programmable interrupt latch bits (P6I–P13I, P17I, P18I) are con-
trolled through the programmable interrupt controller registers (
The descriptions provided are their default source. For information on
their optional use, see "Programmable Interrupt Priority Control Regis-
ters" in the product related hardware reference.
A-30
Definition
User Software Interrupt 0. An SFT0I occurs when a program sets
(= 1) this bit.
User Software Interrupt 1. See SFT01.
User Software Interrupt 2. See SFT01.
User Software Interrupt 3. See SFT01. Lowest priority.
). The register indicates latch status, select masking,
LIRPTL
LIRPTL
bits in the
LIRPTL
ADSP-2126x SHARC Processor Hardware Reference
Figure A-9
register.
register, and the entire
and Table A-10 pro-
register
IMASKP
).
PICRx