Dma Controller Operation - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

• Figure A-73 on page A-169
• Figure A-74 on page A-170
The DMA controller in the ADSP-2126x maintains the status informa-
tion of the channels in each of the peripherals registers,
, and
DAI_STAT
at the following locations.
• Bit definitions for the
Configuration (SPIDMAC) Register" on page
• Bit definitions for the
Multichannel Control Registers (SPMCTLxy)" on page
• Bit definitions for the
Control Register (PPCTL)" on page
• Bit definitions for the
Figure A-70 on page

There is a one cycle latency between a change in DMA channel sta-
tus and the status update in the corresponding register.

If chaining is enabled on a DMA channel, programs should not use
polling to determine channel status as it can provide inaccurate
information. In this case, the DMA appears inactive if it is sampled
while the next transfer control block (TCB) is loading.

DMA Controller Operation

There are two methods you can use to start DMA sequences: chaining and
non-chaining.
Non-chained DMA. To start a new DMA sequence after the current one
is finished, a program must first clear the DMA enable bit, write new
7-8
. More information on these registers can be found
SPIDMAC
SPIDMAC
SPMCTLxy
PPCTL
DAI_STAT
A-162.
ADSP-2126x SHARC Processor Hardware Reference
lists all the bits in
lists all the bits in
register are illustrated in
register are illustrated in
register are illustrated in
A-108.
register are illustrated in
.
DAI_IRPTL_H
.
DAI_IRPTL_L
,
SPMCTLxy PPCTL
"SPI DMA
A-103.
"SPORT
A-79.
"Parallel Port
,