Mode Control - Analog Devices adsp-2100 Manual

Syntax:
ENA
DIS
Example:
DIS AR_SAT, ENA M_MODE;
Description:
Enables (ENA) or disables (DIS) the designated processor
mode. The corresponding mode status bit in the mode status register
(MSTAT) is set for ENA mode and cleared for DIS mode. At reset, MSTAT
is set to zero, meaning that all modes are disabled. Any number of modes
can be changed in one cycle with this instruction. Multiple ENA or DIS
clauses must be separated by commas.
MSTAT Bits:
SEC_REG
0
BIT_REV
1
AV_LATCH
2
AR_SAT
3
M_MODE
4
TIMER
5
G_MODE
6
The data register bank select bit (SEC_REG) determines which set of data
registers is currently active (0=primary, 1=secondary).
The bit-reverse mode bit (BIT_REV), when set to 1, causes addresses
generated by Data Address Generator #1 to be output in bit reversed
order.
The ALU overflow latch mode bit (AV_LATCH), when set to 1, causes the
AV bit in the arithmetic status register to stay set once an ALU overflow
occurs. In this mode, if an ALU overflow occurs, the AV bit will be set and
will remain set even if subsequent ALU operations do not generate
overflows. The AV bit can only be cleared by writing a zero into it directly
over the DMD bus.
BIT_REV
AV_LATCH
AR_SAT
SEC_REG
G_MODE
M_MODE
TIMER
Alternate Register Data Bank
Bit-Reverse Mode on Address Generator #1
ALU Overflow Status Latch Mode
ALU AR Register Saturation Mode
MAC Result Placement Mode
Timer Enable
Enables GO Mode
(instruction continues on next page)
MISC

MODE CONTROL

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