Sticky Status Registers (Stkyx And Stkyy) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Core Registers

Sticky Status Registers (STKYx and STKYy)

These are non memory-mapped, universal, system registers (
). Each processing element has its own
Sreg
ter indicates status for PEx operations and some program sequencer stacks.
The register only indicates status for PEy operations.
STKYy

bits do not clear themselves after the condition they flag is no
STKY
longer true. They remain "sticky" until cleared by the program.
The processor sets a
processor sets the
in the
AZ ASTAT
does not cause an underflow. The
clears the
STKY
rupt's corresponding
the condition. For example, an ISR for a floating-point underflow excep-
tion interrupt (
beginning of the
bit information for both the
A-16
bit in response to a condition. For example, the
STKY
bit in the
AUS STKY
register. The processor clears
bit. Interrupt service routines (ISRs) must clear their inter-
bit so the processor can detect a reoccurrence of
STKY
) clears the
FLTUI AUS
routine.Figure A-5,
STKYx
ADSP-2126x SHARC Processor Hardware Reference
register. The
STKY
register when an ALU underflow set
if the next ALU operation
AZ
bit remains set until a program
AUS
bit in the register near the
STKY
Figure A-6, and
and registers.
STKYy
and
Ureg
regis-
STKYx
Table A-5 provide