Setting Up Dma On Sport Channels - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Moving Data Between SPORTS and Internal Memory
( = 1), the transmit and receive interrupts are generated for the 32-bit
PACK
packed words, not for each 16-bit word.
The following sections present an overview of serial port DMA operations;
additional details are covered in
• For information on SPORT DMA Channel Setup, see
Transmit and Receive Channel Order (FRFS)" on page
• For information on SPORT DMA Parameter Registers, see
ing Transmit and Receive Channel Order (FRFS)" on page
• For information on SPORT DMA Chaining, see
Chaining" on page

Setting Up DMA on SPORT Channels

Each SPORT DMA channel has an Enable bit (
Control register. When DMA is disabled for a particular channel,
SPCTLx
the SPORT generates an interrupt every time it receives a data word or
whenever there is a vacancy in the transmit buffer. For more information,
see "Single Word Transfers" on page
Each channel also has a DMA Chaining Enable bit (
in its control register.
SPCTLx
To set up a serial port DMA channel, write a set of memory buffer param-
eters to the SPORT DMA parameter registers as shown in
9-68
the"Memory" in Chapter 5,
9-73.
9-73.
ADSP-2126x SHARC Processor Hardware Reference
Memory.
"Selecting
9-16.
"SPORT DMA
and
SDEN_A SDEN_B)
and
SCHEN_A SCHEN_B)
Table 9-9.
"Select-
9-16.
in its