Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 495

Table 11-1. Serial Modes
Bit Field Values
IDP_SMODEx
000
001
010
011
100
101
110
111
The polarity of left-right encoding is independent of the serial mode frame
sync polarity selected in
2
that I S mode uses a
(left) channel, and Left-justified Sample Pair mode uses a
(left-right) signal to dictate the first (left) channel of each frame. In either
mode, the left channel has bit 3 set (= 1) and the right channel has bit 3
cleared (= 0).
Figure 11-4 shows the relationship between frame sync, serial clock, and
Left-justified Sample Pair data.
Figure 11-5 shows the relationship between frame sync, serial clock, and
2
I S data.
ADSP-2126x SHARC Processor Hardware Reference
Mode
Left-justified Sample Pair
2
I S
Reserved
Reserved
Right-justified Sample Pair 24 bits
Right-justified Sample Pair 20 bits
Right-justified Sample Pair 18 bits
Right-justified Sample Pair 16 bits
for that channel
IDP_SMODE
frame sync (left-right) signal to dictate the first
LOW
Input Data Port
(Table 11-1). Note
frame sync
HIGH
11-5