I 2 S Mode Control Bits; Setting The Internal Serial Clock And Frame Sync Rates; I 2 S Control Bits - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPORT Operation Modes
2
I S Mode Control Bits
Several bits in the
operation:
• Operation mode, Master mode enable (
• Word length (
• SPORT enable (
For more information, see "Serial Port Registers" on page A-69.

Setting the Internal Serial Clock and Frame Sync Rates

The serial clock rate (
bit field in the
2
I S Control Bits
Table 9-8 on page 9-63
Left-justified Sample Pair mode which can be invoked by setting
= 1,
OPMODE LAFS

If
FRFS
operation (
Several bits in the
2
I S operation:
• Channel enable (
• Word length (
2
• I S channel transfer order (
• Master mode enable (
9-20
Control register enable and configure I
SPCTLx
)
SLEN
and
SPEN_A
value) for internal clocks can be set using a
CLKDIV
register. For details, see
CLKDIV
shows that I
= 0, and = 0.
FRFS
= 1, the Tx/Rx is on the right channel first. For normal I
= 0), the Tx/Rx starts on the left channel first.
FRFS
register Control register enable and configure
SPCTLx
or
SPEN_A
)
SLEN
MSTR
ADSP-2126x SHARC Processor Hardware Reference
OPMODE
)
SPEN_B
Figure 9-8 on page
2
S mode is simply a subset of the
)
SPEN_B
)
FRFS
)
2
S mode
)
9-63.
2
S