Other Recommendations And Suggestions - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Designing for High Frequency Operation
Jitter should be kept to an absolute minimum. High frequency jitter on
the clock to the processor may result in abbreviated internal cycles.
FREQUENCY 1
Figure 15-5. Reducing Clock Jitter and Ring

Never share a clock buffer IC with a signal of a different clock fre-
quency. This introduces excessive jitter.
As shown in Figure
different frequencies as physically separate as possible. The clock supplied
to the processor must have a rise time of 3 ns or less and must meet or
exceed a high and low voltage of 2 V and 0.4 V, respectively.

Other Recommendations and Suggestions

• Use more than one ground plane on the PCB to reduce crosstalk.
Be sure to use lots of vias between the ground planes. One V
plane for each supply is sufficient. These planes should be in the
center of the PCB.
• To reduce crosstalk, keep critical signals such as clocks, strobes,
and bus requests on a signal layer next to a ground plane and away
from or layout perpendicular to other non-critical signals.
• If possible, position the processors on both sides of the board to
reduce area and distances.
• To allow better control of impedance and delay, and to reduce
crosstalk, design for lower transmission line impedances.
15-16
CLOCK
15-5, keep the portions of the system that operate at
ADSP-2126x SHARC Processor Hardware Reference
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ADSP-2126x
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