Interrupt-Driven Transfers; Starting An Interrupt-Driven Transfer - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

FIFO to Memory Data Transfer
• Eight dedicated DMA channels can sort and transfer the data into
one buffer per source channel. When the memory buffer is full, the
DMA channel raises an interrupt in the DAI Interrupt Controller.
This method of moving data from the IDP FIFO is described in
"DMA Transfers" on page

Interrupt-Driven Transfers

The output of the FIFO can be directly fetched by reading from the
register. The
IDP_FIFO
the top sample from the FIFO, which is eight locations deep.
As data is read from the
and new data is copied into the
bits (bits 3–0 in the
IDP_NSET
number of entries (N) in the FIFO. When the FIFO fills to a point where
it has more than N words (data in FIFO exceeds the value set in the
bit field, bits 3–0 of
IDP_NSET
ated. This DAI interrupt corresponds to the
eighth interrupt in
interrupt to detect when data needs to be read.

Starting an Interrupt-Driven Transfer

To start an interrupt-driven transfer:
1. Clear and halt FIFO by setting (= 1) and clearing (= 0) the
bit (bit 7 in the
ABLE
2. Set the required values for:
•
IDP_SMODEx
sync format for the serial inputs (I
Pair, or Right-justified Sample Pair Mode).
11-16
11-18.
register is used only to read and remove
IDP_FIFO
register, it is removed from the FIFO
IDP_FIFO
IDP_FIFO
IDP_CTL
IDP_CTL
or
DAI_IRPTL_L DAI_IRPTL_H
register).
IDP_CTL
bits in the
IDP_CTL
ADSP-2126x SHARC Processor Hardware Reference
register. The contents of the
register) represent a threshold
register), a DAI interrupt is gener-
IDP_FIFO_GTN_INT
. The core can use this
register to specify the frame
2
S, Left-justified Sample
bit, the
IDP_EN-