Spi Control Register (Spictl) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

SPI Control Register (SPICTL)

This register's address is 0x1000. The reset value for this register is
0x0400. The SPI Control register (
the SPI system. This register is used to set up SPI configurations such as
selecting the device as a master or slave or determining the data transfer
rate and word size.
SPICTL (0x1000) 31 30 29 28 27 26
(Bits 31–16)
0
Reserved
TXFLSH
Transmit Buffer Flush
1=SPITX Cleared
0=SPITX Not Cleared
RXFLSH
Receive Buffer Flush
1=SPIRX Cleared
0=SPIRX Not Cleared
Figure A-30. SPICTL Register (Upper bits)
A-96
25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
) is used to configure and enable
SPICTL
0 0 0 0 0 0 0
SGN
Sign-extend Data
1=Sign-extend
0=No Sign-extend
SMLS
Seamless Transfer
1=Enable
0=Disable