Table of Contents
Advertisement
bidirectional functionality provides greater flexibility for serial
communications. Further, two SPORTs can be combined to enable
full-duplex, dual-stream communications.
• All serial data signals have programmable receive and transmit
functions and thus have one transmit and one receive data buffer
register (double-buffer) and a bidirectional shift register associated
with each serial data signal. Double-buffering provides additional
time to service the SPORT.
•
-law and A-law compression/decompression hardware compand-
ing on transmitted and received words.
• An internally-generated serial clock and frame sync provide signals
in a wide range of frequencies. Alternately, the SPORT can accept
clock and frame sync input from an external source, as described in
Figure 9-8 on page
• Interrupt-driven, single word transfers to and from on-chip mem-
ory controlled by the processor core, described in
Transfers" on page
• DMA transfers to and from on-chip memory. Each SPORT can
automatically receive or transmit an entire block of data.
• Chained DMA operations for multiple data blocks, see
DMA Processes" on page
• Four operation modes: DSP Standard Serial, Left-justified Sample
Pair, I
Sample Pair, and I
they transmit or receive data simultaneously, sending or receiving
bit 0 on the same edge of the serial clock, bit 1 on the next edge of
the serial clock, and so on. In multichannel mode, SPORT1, 3 or 5
can receive A and B channel data, and SPORT0, 2 or 4 transmits A
and B channel data selectively from up to 128 channels of a TDM
serial bitstream. This mode is useful for H.100/H.110 and other
9-2
9-63.
9-73.
2
S, and multichannel. In standard DSP serial, Left-justified
2
S modes, when both A and B channels are used,
ADSP-2126x SHARC Processor Hardware Reference
7-10.
"Single Word
"Chaining
Advertisement
Table of Contents
