Transmit And Receive Data Buffers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPORT Control Registers and Data Buffers

Transmit and Receive Data Buffers

The transmit buffers (
,
TXSP3A TXSP3B
mit data buffers for SPORT0, SPORT1, SPORT2, SPORT3, SPORT4,
and SPORT5 respectively. These buffers must be loaded with the data to
be transmitted if the SPORT is configured to transmit on the A and B
channels. The data is loaded automatically by the DMA controller or
loaded manually by the program running on the processor core.
The receive buffers (
RXSP3A, RXSP3B
receive data buffers for SPORT0, SPORT1, SPORT2, SPORT3,
SPORT4, and SPORT5 respectively. These 32-bit buffers become active
when the SPORT is configured to receive data on the A and B channels.
When a SPORT is configured as a receiver, the
ters are automatically loaded from the receive shifter when a complete
word has been received. The data is then loaded to internal memory by the
DMA controller or read directly by the program running on the processor
core.

Word lengths of less than 32 bits are automatically right-justified
in the receive and transmit buffers.
The transmit buffers act like a two-location FIFO because they have a data
register plus an Output Shift register. Two 32-bit words may both be
stored in the transmit queue at any one time. When the transmit register is
loaded and any previous word has been transmitted, the register contents
are automatically loaded into the output shifter. An interrupt occurs when
the Output Transmit shifter has been loaded, signifying that the transmit
buffer is ready to accept the next word (for example, the transmit buffer is
not full). This interrupt does not occur when serial port DMA is enabled
or when the corresponding mask bit in the
In non-Multichannel modes (I
Standard Serial modes), the
9-60
,
TXSP0A TXSP0B
, , ,
TXSP4A TXSP4B TXSP5A,
,
RXSP0A RXSP0B
, , ,
RXSP4A RXSP4B
2
S, Left-justified Sample Pair, and DSP
ROVF_A
ADSP-2126x SHARC Processor Hardware Reference
, ,
TXSP1A TXSP1B
and
TXSP5B
, ,
RXSP1A RXSP1B
and
RXSP5A, RXSP5B
RXSPxA
register is set.
LIRPTL
or and
TUVF_A ROVF_B
, ,
TXSP2A TXSP2B
) are the 32-bit trans-
, , ,
RXSP2A RXSP2B
) are the 32-bit
and regis-
RXSPxB
, or
TUVF_B
,