Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 726

I/O Processor Registers
SPIDMAC (0x1084)
Reserved
SPIDMAS
DMA Transfer Status
1=DMA Transfer in Progress
0=DMA Idle
SPIERRS
DMA Error Status
1=Error During Transfer
0=Successful DMA Transfer
SPISx
DMA FIFO Status
00=FIFO Empty 11=FIFO Full
10=FIFO Partially Full
SPIMME
Multimaster Error
1=Error During Transfer
0=Successful Transfer
SPIUNF
Transmit Underflow Error (DMADIR=0)
1=Transmission Error Occurred with DMA
FIFO Empty
0=Successful Transfer
SPIOVF
Receive Overflow Error (DMADIR=1)
1=Error-Data Received with DMA FIFO Full
0=Successful Transfer
Figure A-32. SPIDMAC Register
A-104
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1
0 0 0 0 0 0 0
0
SPICHS
DMA Chain Loading Status
1=DMA Chain Pointer Loading
in Progress
0=DMA Chain Idle
0
0
SPIDEN
DMA Enable
1=DMA Enable
0=DMA Disable
SPIRCV
DMA Write/Read
1=SPI DMA Read
0=SPI DMA Transmit
INTEN
Enable DMA Interrupt on
Transfer
1=Enable
0=Disable
Reserved
SPICHEN
SPI DMA Chaining Enable
1=Enable
0=Disable
Reserved
FIFOFLSH
DMA FIFO Clear
1=Enable
0=Disable
INTERR
Enable Interrupt on Error
1=Enable
0=Disable