High And Low Priority Latches - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

High and Low Priority Latches

In the ADSP-2126x, a pair of registers (
replace functions normally performed by the
ter (
DAI_IRPTL_PRI
are mapped.
Two registers (
eral's version of the
registers provide a way to specify which interrupts to notice and handle,
and which interrupts to ignore. These dual registers function like
does, but with a higher degree of granularity.
Signals from the SRU can be used to generate interrupts. For example,
when
SRU_EXTMISCA2_INT
from the external miscellaneous Channel 2 generates an interrupt. If set to
one, DAI interrupts trigger an interrupt in the core and the interrupt latch
is set. A read of this bit does not reset it to zero. The bit is only set to zero
when the cause of the interrupt is cleared. A DAI interrupt indicates the
source (in this case, external miscellaneous A, Channel 2), and checks the
IVT for an instruction (next operation) to perform.
The 32 interrupt signals within the Interrupt Controller are mapped to
two interrupt signals in the primary Interrupt Controller of the SHARC
core. The
DAI_IRPT_PRI
rupt is mapped to the high or low core interrupt (1 = high priority and 0 =
low priority).
The
DAI_IRPTL_H
interrupt latched for the high priority core interrupt. The
register is a read-only register with bits set for every DAI interrupt latched
for the low priority core interrupt. When a DAI interrupt occurs, the low
or high priority core ISR should interrogate its corresponding register to
determine which of the 32 interrupt sources to service. When the
register is read, the high priority latched interrupts are all
DAI_IRPTL_H
ADSP-2126x SHARC Processor Hardware Reference
) specifies the latch to which each of these interrupts
and
DAI_IRPTL_RE
register. As with the
IMASK
(bit 30) or
register specifies if the Interrupt Controller inter-
register is a read-only register with bits set for every DAI
Digital Audio Interface
DAI_IRPTL_H
register. A single regis-
IRPTL
) replace the DAI periph-
DAI_IRPTL_FE
IMASK
is set to one, any signal
DAI_IRPTL_H
and )
DAI_IRPTL_L
register, these DAI
IMASK
DAI_IRPTL_L
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