8-Bit Access - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Parallel Port Throughput

8-Bit Access

In 8-bit mode, the first data-access (whether a read or a write) always con-
sists of one
ALE
bits of address do not change, each subsequent transfer consists of four
data cycles. The
crosses an 8-bit boundary page, in other words, after every 256 bytes that
are transferred.
For example, if
first byte on a new page takes six core cycles (three for the
three for the data cycle), and the next sequential 255 bytes consume three
core cycles each.
Therefore, the average data rate for a 256 byte page is:
(3 x 255 + 6
CCLK
For a 200 MHz core, this results in:
(200M /sec) x (1 byte/3.008
CCLK
16-Bit Access
In 16-bit mode, every word transfer consists of two
data cycles. Therefore, for every 32-bit word transferred, at least six
cycles are needed to transfer the data plus an additional six
the two cycles, for a total of 12
ALE
bytes). For a 200 MHz core clock, this results in a maximum sustained
data rate device of:
200 MHz /12 = 16.67 Million 32-bit words/sec = 66.6M Bytes/sec
There is a specific case which allows this maximum rate to be exceeded. If
the external address modifier (
8-14
cycle followed by four data cycles. As long as the upper 16
cycle is inserted only when the parallel port address
ALE
, = 0, and the processor is in 8-bit mode. The
PPDUR3 BHC
x 1) / 256 = 3.01 core clock cycles per byte.
CCLK
EMPP
ADSP-2126x SHARC Processor Hardware Reference
) = 66.4M bytes/sec
CCLK
ALE
cycles per 32-bit transfer (four
CCLK
) is set to a stride of zero, then only one
cycle and
ALE
cycles and two
CCLK
cycles for
CCLK