Contents
Frame Sync Outputs ................................................................... 13-4
Frame Sync ........................................................................... 13-4
Phase Shift ................................................................................. 13-7
Pulse Width .......................................................................... 13-9
Bypass Mode ....................................................................... 13-10
Timer Architecture ..................................................................... 14-1
Timer Interrupts ................................................................... 14-4
Enabling a Timer ........................................................................ 14-5
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ADSP-2126x SHARC Processor Hardware Reference
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